1. Field
The present invention relates to a method for the manufacturing of a semiconductor package.
2. Description of the Related Art
The trend in current electronic devices, such as MP3 players, cell phones, and laptops, etc., is towards designs that include numerous semiconductor chips packaged on the main board, such that multiple functions may be performed within an extremely small area, as well as structures that allow miniaturized sizes and facilitated heat release. Accordingly, the semiconductor chips are being given higher degrees of integration, and the sizes of the semiconductor packages are being reduced.
Furthermore, as semiconductor packages are expected to not only provide low thickness, light weight, and small size, but also higher performance and greater systemization, there has also been developed a method of stacking several packages together, so that packages having various functions can be implemented as a single package.
FIG. 1 is a cross-sectional view of a semiconductor package according to the related art, which presents a package-on-package (POP) structure, where a package is stacked again over another package. In order to stack a package over another package having an embedded chip according to the related art, the structure may include metal pads formed around the chip mounted on the lower portion, between the upper layer and lower layer packages, such that the metal pads may connect the upper layer package with the lower layer package.
However, in the semiconductor package according to the related art, the metal pads for mounting the upper layer package may reduce the mounting area, making it difficult to obtain a sufficient space for mounting passive components such as RLC. Also, in stacking the package, warpage that can occur in the packages may pose difficulties in achieving secure stacking.